The present invention is related to semiconductor devices and, more specifically, to a transistor metal gate structure that minimizes non-planarity effects.
As used herein, the term xe2x80x9chigh-k materialxe2x80x9d or xe2x80x9chigh dielectric constant materialxe2x80x9d refers to any material with a dielectric constant that is greater than silicon dioxide. The dielectric constant of silicon dioxide is approximately 3.9.
As the industry moves to high dielectric constant materials due to electrical problems of using a thin silicon dioxide layer, using polysilicon as a gate electrode can result in the depletion of carriers in the polysilicon gate. To alleviate the polysilicon depletion problem, metal gate structures can be used.
One method used to form transistor metal gate structures includes depositing metal layers within a gate trench, meaning a trench where a gate will subsequently be formed, and along the top surface of insulating materials surrounding the gate trench. An etch back or polishing process is used to remove the portions of the metal layers lying outside the gate trench.
When removing the metal layers using chemical mechanical polishing (CMP), dishing can occur across the semiconductor wafer and when using etch back the insulating materials around the gate trench can erode. This results in non-functional devices, which decreases yield. Therefore, there is a need for a semiconductor process that minimizes non-planarity effects when removing the metal layers outside the gate trench.